In order to improve the performance of integrated circuits, it is generally desirable that the clock frequency is as high as possible while maintaining correct circuit functionality. Furthermore, to reduce energy consumption, it also desirable that the supply voltage of the circuit is as low as possible while maintaining correct circuit functionality. Beyond a certain operating point corresponding to a clock frequency and supply voltage limit, the circuit will no longer function correctly. There is however a technical difficulty in detecting when a clock frequency/supply voltage limit has been reached.
An integrated circuit will no longer maintain correct functionality if one or more of its synchronous devices are subjected to timing violations. Synchronous devices include registers, flip-flops, memories and latches. Such devices are generally characterized by a setup-time tS and a hold-time tH that should be respected in order to ensure stability. The setup-time tS defines a time period before a significant clock edge during which the input data of the synchronous device should not change. The hold-time tH defines a time period after a significant clock edge during which the input data should not change. A timing violation occurs if the setup-time or hold-time is not respected.
A static timing analysis of an integrated circuit design can identify one or more critical transmission paths, which are the transmission paths with the longest propagation delays between two synchronous devices in the circuit. The propagation delays on these critical transmission paths are generally used to determine the maximum permitted clock frequency of the circuit.
It is however necessary to allow a safety margin, as the propagation times of data in a given circuit may shift as a result of PVT (process, voltage, temperature) variations. The safety margin is based on the worst case scenario, and a problem is that such a design strategy therefore leads to performance that is far from optimal.
A publication by Y. Kanitake et al. entitled “Possibilities to Miss Predicting Timing Errors in Canary Flip-flops”, IEEE, Jan. 7, 2011, proposes solutions for improving circuit performance by incorporating detection circuits in an integrated circuit that detect when timing violations occur, and controlling the level of the supply voltage accordingly.
A drawback of existing solutions such as the one described by Kanitake et al. is that, to be certain to avoid a timing violation anywhere in the circuit, it is necessary to add a detection circuit to each synchronous device of the circuit, leading to a reduction in circuit performance and a significant increase in cost and silicon area.
There is thus a need in the art for a new solution for improving circuit performance while reducing the number of detection circuits.